Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to multi-layer fan-out wafer level packages and embedded multi-chip assemblies and methods of manufacturing thereof. The method enables the handling of thin substrate materials that typically are not used in multilayer structures in a panel process, and uses a device-last attach or device-almost last attach that minimizes yield losses associated with fine line interconnect from the loss of good devices due to interconnect losses.
State of the art electronics packaging covers a wide range of methods, structures and approaches from wire bond modules to flip chip modules and to embedded chip modules. Wire bonded modules are a mature packaging approach that is low cost but with limited electrical performance. These modules use wires bonded to chip pads to connect the top input/output (I/O) pads of power devices to an interconnect structure such as a metal-insulator-metal substrate such as ceramic, AlN or SiC substrate with patterned metal on top and bottom. An exemplary construction of a prior art wire bond electronics package 10 is illustrated in FIG. 1 with two power semiconductor devices 12 mounted onto a multilayer substrate 14 using die attach material 16—with the multilayer substrate 14 including bond pads 18, buried wiring layers 20, back side wiring 22, dielectric layers 24, microvias 26, and through holes 28. Wire bonds 30 connect die pads 32 located on the active surface 34 of semiconductor devices 12 to selected areas on the multilayer substrate 14, such as bond pads 18. Molding resin 36 encapsulates the semiconductor devices 12 and the wire bonds 18 and exposed portions of multilayer substrate 14. Wire bonds 18 have inherently high inductance, generally high series resistance, current crowning on the bond pads, and micro-cracking within the semiconductor devices 12 near bonding sites.
Prior art flip chip modules experience reduced semiconductor substrate damage as compared to wire bond packages, with flip chip modules using solder bumps that have larger current carrying cross-sections than wire bonds. A general construction of a prior art flip chip electronics package 40 is illustrated in FIG. 2, with two semiconductor devices 12 attached to a multilayer substrate 14. The multilayer substrate 14 includes terminal pads 18, buried wiring layers 20, back side wiring 22, dielectric layers 24, microvias 26 and through holes 28. The two semiconductor devices 12 are attached to terminal pads 18 by means of flip chip solder bumps 42. Molding resin 36 encapsulates the semiconductor devices 12. While flip chip modules such as that illustrated in FIG. 2 provide some advantages over wire bond technology, the flip chip solder bumps have poor electrical conductivity, are susceptible to solder fatigue, and provide a very poor thermal cooling pathway.
Embedded chip modules and Fan-Out Wafer Level Packages (WLPs) are packaging approaches that address the limitations of wire bond and flip chip packages by eliminating wire bonds and solder bumps and replacing them with direct metallization contacts. Embedded chip modules and Fan-Out WLPs are moving into the mainstream of microelectronics packaging for low and mid-complexity semiconductor devices, with these approaches being driven by the latest portable electronics devices, such as smart phones, as each new generation of smart phones puts more function into a smaller space with the requirement that the electronics consume less power. Embedded chip modules combine multiple electronic devices, such as semiconductor chips, capacitors, resistors and/or inductors in a common package using direct chip interconnects. Fan-Out WLPs embed one semiconductor chip under an interconnect structure that fans out the chip I/O terminals from the restricted area of the chip surface to a larger footprint. This allows device I/O pitch to be relaxed to a larger I/O terminal pitch that facilitates attachment to a printed circuit board (PCB).
An example embedded device module 46 is illustrated in FIG. 3A, such as might be fabricated using General Electric Company's power overlay (POL) technology. In the embedded device module 46 of FIG. 3, two semiconductor devices 12 are attached to an overlay dielectric structure 14. The overlay dielectric structure 14 has two dielectric layers 48 with first micro-via connections 50 formed through the lowest of dielectric layers 48 to die pads 32 of semiconductor devices 12 and connecting them to buried wiring layer 44, and with second microvia connections 52 formed through the upper dielectric layer 48 to buried wiring layer 20 and connecting to topside wiring layer 54. Molding resin 36 encapsulates the semiconductor devices 12.
A general construction of a prior art Fan-Out Wafer Level Package (WLP) 56 is depicted in FIG. 3B, with one semiconductor device 11 molded into a resin material 36. An overlay dielectric structure 14 lies over the active surface 34 of the semiconductor device 12 and the top surface 58 of resin material 36. Generally, the process of forming the Fan-Out WLP 56 starts with embedding semiconductor device 12 in resin material 36, with top surface 58 of resin material 36 level with active surface 34 of semiconductor device 12. A first overlay dielectric layer 14a is then applied over the active surface 34 of semiconductor device 12 and the top surface 58 of resin material 36. Next, microvias are formed in the first overlay dielectric layer 14a to die pads 32 and optionally, to optional feed through conductors 60 that may be embedded in the resin material 36. First wiring layer 20 is applied to the first overlay dielectric layer 14a and into the microvias to form first microvia connections 50 to die pads 32. Second overlay dielectric layer 14b is applied to first overlay dielectric layer 14a and first wiring layer 20. Microvias are then formed in the second overlay dielectric layer 14b to portions of first wiring layer 20. Top side wiring layer 54 is applied to the second overlay dielectric layer 14b and into the microvias and forms second microvia connections 52 to exposed portions of first wiring layer 20. Additional overlay dielectric layers and wiring layers can be applied as needed for more complex, higher I/O pad count devices.
Beneficially, an embedded device module provides reduced parasitics (e.g., resistance capacitance and inductance), superior thermal performance, faster operation, and lower power dissipation than wire bond modules or flip chip modules, but is also more complex, less mature, and more costly with lower module yields, while Fan-Out WLPs allow a device I/O pitch to be relaxed to a larger I/O terminal pitch, to facilitate attachment of the device to a printed circuit board (PCB) and thereby reduce PCB complexity, lower its costs, and increase its yields. However, it is recognized that one of the key limitations with embedded device technology and Fan-Out WLP into more complex devices with higher I/O count, is the yield loss associated with the interconnect structure. The interconnect structure in embedded and Fan-Out devices is fabricated after the electronic devices have been incorporated into the structure. All interconnect structures have yield losses caused by opens, shorts, and latent defects. These defects get worse when line widths, line spacing, and via diameters are reduced as device I/O count increase. Wire bond modules and flip chip modules are chips last structures, where the chips are only mounted onto the interconnect substrate if the substrate is free of interconnect defects, and thus are not committed to substrates with bad interconnects. With chips first embedded chip modules and Fan-Out WLPs, the chip is mounted to the interconnect structure before the interconnect structure is complete and tested to verify that it is defect free. A defect that occurs after the chip is committed will cause the chip to be discarded along with the defective interconnect structure, resulting in a higher chip yield loss that chip last approaches. The interconnect yield loss inherently increases as the complexity of the chip and the required interconnect structure increase, as happens with chips with higher I/O counts.
Accordingly, it would be desirable to provide a new interconnect structure and associated manufacturing process that can provide the advantages of an embedded chip module and/or a Fan-Out WLP device without the costly loss of good chip due to a defective interconnect structure.